Currently, frequency synthesizers are used to generate signals of variable frequencies on the basis of two types of architecture, a phase locked loop, denoted PLL, and a delay locked loop, denoted DLL.
It is possible to cite for example the publication “A Mixed PLL/DLL Architecture for low jitter clock generation (2004 IEEE, Authors: Yong-Cheol Bae and Gu-Yeon Wei, published on 23-26 May 2004)” which discloses a system for decreasing the temporal drift of a signal using an architecture of PLL type and of DLL type. The system comprises an integer divider for generating frequencies of the output signal a multiple of the clock frequency, but it does not make it possible to generate sufficiently accurate frequencies. Furthermore, it uses a second-order loop filter, thereby rendering the system slow in respect of the generation of the output signal.
It is also possible to cite the publication “Low-Spur, Low-Phase-Noise Clock Multiplier Based on a Combination of PLL and Recirculating DLL With Dual-Pulse Ring Oscillator and Self-Correcting Charge Pump (2008 IEEE, Author: Sander L. J. Gierkink, published on 10 Dec. 2008)” which discloses a system for synthesizing signals of frequency a multiple of a clock frequency having low phase noise comprising a combination of a PLL and of a DLL. But neither does this document describe a means for obtaining still more accurate frequencies. Moreover, in this system, the oscillator of the DLL is activated permanently by the edges of the clock signal, this having a tendency to slow down the generation of the output signal.
There is therefore proposed a device and a method for generating signals having a sufficiently accurate frequency while being stable. There is also proposed a device and a method which are fast.